Mr. Kumar Sheelvardhan

Kumar Sheelvardhan is serving as Senior Lecturer at NAMTECH, Ahmedabad. He going to complete his Ph.D. from the Department of Electronics and Communication Engineering, IIT Roorkee. His research focuses on scientific machine learning for semiconductor devices: physics-informed neural networks and knowledge-based neural networks that make compact modeling of nanoscale transistors faster without giving up accuracy. He completed his M.Tech in Electrical Engineering at NIT Rourkela and his B.Tech in Electronics and Communication Engineering at NEHU Shillong before joining IIT Roorkee. He also worked on the position of Technical Officer and Junior Technical Superintendent in the IIIT Bhagalpur.

His work covers compact modeling for FinFETs, gate-all-around transistors, and STT-MRAM devices, carried out largely under the Semiconductor Research Corporation program with industry partners including GlobalFoundries and Siemens EDA. He spent time as an intern at GlobalFoundries India, working on machine learning-based parameter extraction, and contributed to the development and release of the BSIM-MTJ-BDMC compact model for BSIM-partnered industries.

He has authored or co-authored papers published in journals including IEEE Transactions on Electron Devices, Engineering Applications of Artificial Intelligence, and IEEE Transactions on Artificial Intelligence. He received the Prime Minister’s Research Fellowship (2023-2025) and a SERB International Travel Grant (2023).

December 2021–September 2026 (Expected) | Ph.D. in Electronics & Communication Engineering

IIT Roorkee, Uttarakhand, India

2012–2014 | M.Tech. in Electrical Engineering

NIT Rourkela, Odisha, India

2007–2011 | B.Tech. in Electronics & Communication Engineering

North Eastern Hill University Shillong, Meghalaya, India

August 2026–Present | Senior Lecturer

NAMTECH’s School of Manufacturing Design & AI

June 2023–March 2024 | Intern

GlobalFoundries India, Bangalore, India

July 2018–December 2021 | Junior Technical Superintendent

IIIT Bhagalpur, Bihar, India

July 2017–June 2018 | Technical Officer Grade II

IIIT Bhagalpur, Bihar, India

  1. Journal Publications (First Author):
  2. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy, and A. Dasgupta, “Machine Learning Augmented Compact Modeling for Simultaneous Improvement in Computational Speed and Accuracy,” IEEE Transactions on Electron Devices, vol. 71, no. 1, pp. 239-245, 2024.
  3. Sheelvardhan, S. Guglani, A. Dubey, S. Dubey, S. Ramaswamy, V. Subramanian, K. Anderson, G. Workman, S. Roy, and A. Dasgupta, “Scientific Machine Learning for Generic Compact Model Parameter Extraction of Nanoscale Transistors,” Engineering Applications of Artificial Intelligence, vol. 162, Part B, 2025.
  4. Sheelvardhan, S. Roy, and A. Dasgupta, “HyPIN-ODE: A Physics-Informed Neural ODE for Fast STT-MRAM Magnetization Modeling,” IEEE Access, 2026 (under review).
  5. Sheelvardhan, A. Kumar, M. Shukla, S. Roy, and A. Dasgupta, “Physics-Regularized Neural Network Surrogate with Dual Evolutionary Optimization for Pareto-Optimal FeFET Memory Design,” IEEE Transactions on Nanotechnology, 2026 (under review).
  6. Co-author Publications:
  7. Ehteshamuddin, K. Sheelvardhan, A. Kumar, S. Guglani, S. Roy, and A. Dasgupta, “Machine Learning-Assisted Multiobjective Optimization of Advanced Node Gate-All-Around Transistor for Logic and RF Applications,” IEEE Transactions on Electron Devices, vol. 71, no. 2, pp. 976-982, 2024.
  8. Parandiyal, A. Kumar, M. Ehteshamuddin, A. Singh, K. Sheelvardhan, S. Ray, A. Somani, S. Roy, and A. Dasgupta, “Metalearning Based Adaptive Compact Modeling Framework for Advanced Transistors Across Technology Nodes,” IEEE Transactions on Artificial Intelligence, vol. 6, no. 10, pp. 2810-2818, 2025.
  9. Singh, M. Ehteshamuddin, A. Kumar, M. Shukla, D. Pyngrope, S. Parandiyal, K. Sheelvardhan, A. K. Behera, S. Ray, A. Somani, S. Roy, and A. Dasgupta, “Complete Charge-Based Artificial Neural Network Augmented Compact Model for Common Multi-Gate FETs,” IEEE Transactions on Electron Devices, vol. 73, pp. 2593-2599, 2026.
  10. Farooq Dar, Gagan, K. Sheelvardhan, A. Kumar, T. Pramanik, S. Salahuddin, C. Hu, and A. Dasgupta, “A Compact Model for Perpendicular STT-MRAM Incorporating Free and Pinned Layer Thickness Dependence, Accurate Bias Dependence, and Real-Time 3-D Switching Dynamics,” IEEE Transactions on Electron Devices, vol. 72, no. 8, pp. 4123-4130, 2025.
  11. Conference Papers / Talks:
  12. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy, and A. Dasgupta, “Variability Aware FET Model with Physics Knowledge Based Machine Learning,” IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, South Korea, 2023, pp. 1-3.
  13. Sheelvardhan, S. Parandiyal, M. Ehteshamuddin, A. Kumar, S. Roy, and A. Dasgupta, “Neural Network Augmented Physics Based Hybrid Compact Model for Computational Efficiency Improvement,” IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024.
  14. Sheelvardhan, D. Pyngrope, S. Roy, and A. Dasgupta, “Extreme Learning Machine-Based Unified Modeling of All Multi-Gate Semiconductor Devices,” International Workshop on Physics of Semiconductor Devices (IWPSD), Roorkee, India, 2025.
  15. Sheelvardhan, D. Pyngrope, S. Roy, and A. Dasgupta, “Fast and Accurate Device Modeling: Extreme Learning Machine for Multi-Gate Transistors,” IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2026, pp. 1-3.
  16. Sheelvardhan, M. Ehteshamuddin, S. Roy, and A. Dasgupta, “Machine Learning Augmented Hybrid BSIM-CMG Compact Model for Increased Simulation Speed,” International Workshop on Physics of Semiconductor Devices (IWPSD), Chennai, India, 2023.
  17. Parandiyal, A. Singh, K. Sheelvardhan, S. Guglani, M. Ehteshamuddin, S. Roy, and A. Dasgupta, “An Efficient Variability-Aware Control Variate-Assisted Neural Network Model for Advanced Nanoscale Transistors,” IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-4.
  18. Shukla, A. Kumar, M. Ehteshamuddin, K. Sheelvardhan, and A. Dasgupta, “Novel Charge Partitioning Compact Model Including Field-Dependent Mobility Degradation Effect for Nanoscale MOSFETs,” IEEE Workshop on Physics of Semiconductor Devices (IWPSD), Chennai, India, 2023.
  19. Singh, S. Parandiyal, K. Sheelvardhan, M. Ehteshamuddin, S. Roy, and A. Dasgupta, “Using Control Variates for Improved Efficiency of Neural Network Based Modeling of Advanced Transistors,” Semiconductor Research Corporation TECHCON, Austin, TX, USA, 2024.
  • Compact modeling of semiconductor devices (BSIM-CMG, BSIM-IMG, BSIM-MTJ)
  • Physics-informed neural networks (PINNs) and knowledge-based neural networks for device modeling
  • Scientific machine learning and extreme learning machines for nanoscale transistors
  • Variability-aware modeling of FinFET and gate-all-around (GAA) transistors
  • STT-MRAM and magnetic tunnel junction modeling
  • Parameter extraction and simulation speed-up for SPICE-compatible compact models

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